Patent Document 1 (Japanese Patent Application Publication No. 2002-353444) discloses a semiconductor device including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). This semiconductor device includes a p-type semiconductor substrate (semiconductor layer). In a surface portion of the semiconductor substrate, a p-type channel region (body region) and an n-type drain-drift region are formed. The channel region is formed inside with an n-type source region, and the drain-drift region is formed inside with an n-type drain region. Between the source region and the drain region, a gate electrode layer opposed to the channel region across a gate insulating film is formed.
On the semiconductor substrate, an interlayer insulating film is formed. On the interlayer insulating film, a molding resin (resin) is formed. In the interlayer insulating film, a source electrode layer that is electrically connected to the source region and a drain electrode layer that is electrically connected to the drain region are formed. To the source electrode layer, a source electrode serving also as a field plate is electrically connected, and to the drain electrode layer, a drain electrode serving also as a field plate is electrically connected.